Example test code for the Core-and64 patch

The output code without the patch is on the left.

   1 void bar (long long, long long);
   2 
   3 void
   4 foo (long long a)
   5 {
   6     bar (a&1, a);
   7 }
   8 
   9 void
  10 foo2 (long long a)
  11 {
  12     bar (a&~0x100000001, a);
  13 }
  14 
  15 long long
  16 and (long long a, long long b)
  17 {
  18   return a & b;
  19 }
  20 
  21 long long
  22 anddi_zesidi_di (unsigned int a, long long b)
  23 {
  24   return a & b;
  25 }
  26 
  27 long long
  28 anddi_sesdi_di (int a, long long b)
  29 {
  30   return a & b;
  31 }
  32 
  33 long long
  34 anddi_notdi_di (long long a, long long b)
  35 {
  36   return ~a & b;
  37 }
  38 
  39 long long
  40 anddi_notzesidi_di (unsigned int a, long long b)
  41 {
  42   return ~((unsigned long long)a) & b;
  43 }
  44 
  45 long long
  46 anddi_notsesidi_di (int a, long long b)
  47 {
  48   return ~((long long)a) & b;
  49 }
  50 
  51 
  52 long long
  53 not (long long a)
  54 {
  55   return ~a;
  56 }
  57 
  58 long long
  59 or (long long a, long long b)
  60 {
  61   return a | b;
  62 }
  63 
  64 long long
  65 or_const (long long a)
  66 {
  67   return a | 10;
  68 }
  69 
  70 long long
  71 iordi_zesidi_di (unsigned int a, long long b)
  72 {
  73   return a | b;
  74 }
  75 
  76 long long
  77 iordi_sesidi_di (int a, long long b)
  78 {
  79   return a | b;
  80 }
  81 
  82 long long
  83 xor (long long a, long long b)
  84 {
  85   return a ^ b;
  86 }
  87 
  88 long long
  89 xor_const (long long a)
  90 {
  91   return a ^ 10;
  92 }
  93 
  94 long long
  95 xordi_zesidi_di (unsigned int a, long long b)
  96 {
  97   return a ^ b;
  98 }
  99 
 100 long long
 101 xordi_sesidi_di (int a, long long b)
 102 {
 103   return a ^ b;
 104 }

foo:
    mov     r2, r0               | mov     r2, r0
    mov     r3, r1               | mov     r3, r1
    movs    r0, #1               | and     r0, r0, #1
    movs    r1, #0               | movs    r1, #0
    ands    r0, r0, r2           |
    ands    r1, r1, r3           |
    b       bar                  | b       bar

foo2:
    mov     r2, r0               | mov     r2, r0
    mov     r3, r1               | mov     r3, r1
    mvn     r0, #1               | bic     r0, r0, #1
    mvn     r1, #1               | bic     r1, r1, #1
    ands    r0, r0, r2           |
    ands    r1, r1, r3           |
    b       bar                  | b       bar

and:
    ands    r2, r2, r0           | ands    r0, r0, r2
    ands    r3, r3, r1           | ands    r1, r1, r3
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

anddi_zesidi_di:
    ands    r2, r2, r0           | ands    r0, r0, r2
    movs    r3, #0               | movs    r1, #0
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

anddi_sesdi_di:
    and     r3, r3, r0, asr #31  | mov     r1, r0
    ands    r2, r2, r0           | ands    r0, r0, r2
    mov     r0, r2               | and     r1, r3, r1, asr #31
    mov     r1, r3               |
    bx      lr                   | bx      lr

anddi_notdi_di:
    bic     r2, r2, r0           | bic     r0, r2, r0
    bic     r3, r3, r1           | bic     r1, r3, r1
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

anddi_notzesidi_di:
    bic     r2, r2, r0           | bic     r0, r2, r0
    mov     r1, r3               | mov     r1, r3
    mov     r0, r2               |
    bx      lr                   | bx      lr

anddi_notsesidi_di:
    bic     r3, r3, r0, asr #31  | mov     r1, r0
    bic     r2, r2, r0           | bic     r0, r2, r0
    mov     r0, r2               | bic     r1, r3, r1, asr #31
    mov     r1, r3               |
    bx      lr                   | bx      lr

not:
    mvns    r2, r0               | mvns    r0, r0
    mvns    r3, r1               | mvns    r1, r1
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

or:
    orrs    r2, r2, r0           | orrs    r0, r0, r2
    orrs    r3, r3, r1           | orrs    r1, r1, r3
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

or_const:
    movs    r2, #10              | orr     r0, r0, #10
    movs    r3, #0               |
    orrs    r2, r2, r0           |
    orrs    r3, r3, r1           |
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

iordi_zesidi_di:
    orrs    r2, r2, r0           | orrs    r0, r0, r2
    mov     r1, r3               | mov     r1, r3
    mov     r0, r2               |
    bx      lr                   | bx      lr

iordi_sesidi_di:
    orr     r3, r3, r0, asr #31  | mov     r1, r0
    orrs    r2, r2, r0           | orrs    r0, r0, r2
    mov     r0, r2               | orr     r1, r3, r1, asr #31
    mov     r1, r3               |
    bx      lr                   | bx      lr

xor:
    eors    r2, r2, r0           | eors    r0, r0, r2
    eors    r3, r3, r1           | eors    r1, r1, r3
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

xor_const:
    movs    r2, #10              | eor     r0, r0, #10
    movs    r3, #0               |
    eors    r2, r2, r0           |
    eors    r3, r3, r1           |
    mov     r0, r2               |
    mov     r1, r3               |
    bx      lr                   | bx      lr

xordi_zesidi_di:
    eors    r2, r2, r0           | eors    r0, r0, r2
    mov     r1, r3               | mov     r1, r3
    mov     r0, r2               |
    bx      lr                   | bx      lr

xordi_sesidi_di:
    eor     r3, r3, r0, asr #31  | mov     r1, r0
    eors    r2, r2, r0           | eors    r0, r0, r2
    mov     r0, r2               | eor     r1, r3, r1, asr #31
    mov     r1, r3               |
    bx      lr                   | bx      lr

AndrewStubbs/Sandbox/core-and64 (last modified 2012-05-22 15:11:53)