Attachment 'core-and64.patch'

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   1 2012-05-21  Andrew Stubbs  <ams@codesourcery.com>
   2 
   3 	gcc/
   4 	* config/arm/arm.md (anddi3, iordi3, xordi3): Expand to two SImode
   5 	operands unless NEON is enabled.
   6 	(one_cmpldi2): Rename to one_cmpldi2_neon, and create a new
   7 	define_expand named one_cmpldi2 similar to anddi3.
   8 	(anddi3_insn, anddi_sesdi_di, anddi_notdi_di, anddi_notzesidi_di,
   9 	anddi_notsesidi_di, iordi3_insn, iordi_zesidi_di, iordi_sesidi_di,
  10 	xordi3_insn, xordi_zesidi_di, xordi_sesidi_di): Delete.
  11 	(zero_extend<mode>di2, extend<mode>di2): Convert to expanders.
  12 	Insert the code from the zero_extend/sign_extend splitter.
  13 	(various nameless splitters): Remove some DI -> SImode splits.
  14 	Convert other DI -> SI mode splitters to just call expanders.
  15 	* config/arm/iterators.md (mode_name): New mode attrubute.
  16 	(qhs_zextenddi_cond, qhs_sextenddi_cond): Delete.
  17 	* config/arm/neon.md (zero_extend<mode>di2_neon): New insn.
  18 	(extend<mode>di2_neon): Likewise.
  19 
  20 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
  21 index 351e83a..70e481d 100644
  22 --- a/gcc/config/arm/arm.md
  23 +++ b/gcc/config/arm/arm.md
  24 @@ -2009,6 +2009,7 @@
  25  
  26  ;; Split up simple DImode logical operations.  Simply perform the logical
  27  ;; operation on the upper and lower halves of the registers.
  28 +;; This is only used for anddi3_neon, iordi3_neon, xordi3_neon
  29  (define_split
  30    [(set (match_operand:DI 0 "s_register_operand" "")
  31  	(match_operator:DI 6 "logical_binary_operator"
  32 @@ -2030,111 +2031,26 @@
  33    }"
  34  )
  35  
  36 -(define_split
  37 -  [(set (match_operand:DI 0 "s_register_operand" "")
  38 -	(match_operator:DI 6 "logical_binary_operator"
  39 -	  [(sign_extend:DI (match_operand:SI 2 "s_register_operand" ""))
  40 -	   (match_operand:DI 1 "s_register_operand" "")]))]
  41 -  "TARGET_32BIT && reload_completed"
  42 -  [(set (match_dup 0) (match_op_dup:SI 6 [(match_dup 1) (match_dup 2)]))
  43 -   (set (match_dup 3) (match_op_dup:SI 6
  44 -			[(ashiftrt:SI (match_dup 2) (const_int 31))
  45 -			 (match_dup 4)]))]
  46 -  "
  47 -  {
  48 -    operands[3] = gen_highpart (SImode, operands[0]);
  49 -    operands[0] = gen_lowpart (SImode, operands[0]);
  50 -    operands[4] = gen_highpart (SImode, operands[1]);
  51 -    operands[1] = gen_lowpart (SImode, operands[1]);
  52 -    operands[5] = gen_highpart (SImode, operands[2]);
  53 -    operands[2] = gen_lowpart (SImode, operands[2]);
  54 -  }"
  55 -)
  56 -
  57 -;; The zero extend of operand 2 means we can just copy the high part of
  58 -;; operand1 into operand0.
  59 -(define_split
  60 -  [(set (match_operand:DI 0 "s_register_operand" "")
  61 -	(ior:DI
  62 -	  (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
  63 -	  (match_operand:DI 1 "s_register_operand" "")))]
  64 -  "TARGET_32BIT && operands[0] != operands[1] && reload_completed"
  65 -  [(set (match_dup 0) (ior:SI (match_dup 1) (match_dup 2)))
  66 -   (set (match_dup 3) (match_dup 4))]
  67 -  "
  68 -  {
  69 -    operands[4] = gen_highpart (SImode, operands[1]);
  70 -    operands[3] = gen_highpart (SImode, operands[0]);
  71 -    operands[0] = gen_lowpart (SImode, operands[0]);
  72 -    operands[1] = gen_lowpart (SImode, operands[1]);
  73 -  }"
  74 -)
  75 -
  76 -;; The zero extend of operand 2 means we can just copy the high part of
  77 -;; operand1 into operand0.
  78 -(define_split
  79 -  [(set (match_operand:DI 0 "s_register_operand" "")
  80 -	(xor:DI
  81 -	  (zero_extend:DI (match_operand:SI 2 "s_register_operand" ""))
  82 -	  (match_operand:DI 1 "s_register_operand" "")))]
  83 -  "TARGET_32BIT && operands[0] != operands[1] && reload_completed"
  84 -  [(set (match_dup 0) (xor:SI (match_dup 1) (match_dup 2)))
  85 -   (set (match_dup 3) (match_dup 4))]
  86 -  "
  87 -  {
  88 -    operands[4] = gen_highpart (SImode, operands[1]);
  89 -    operands[3] = gen_highpart (SImode, operands[0]);
  90 -    operands[0] = gen_lowpart (SImode, operands[0]);
  91 -    operands[1] = gen_lowpart (SImode, operands[1]);
  92 -  }"
  93 -)
  94 -
  95  (define_expand "anddi3"
  96    [(set (match_operand:DI         0 "s_register_operand" "")
  97  	(and:DI (match_operand:DI 1 "s_register_operand" "")
  98  		(match_operand:DI 2 "neon_inv_logic_op2" "")))]
  99    "TARGET_32BIT"
 100 -  ""
 101 -)
 102 -
 103 -(define_insn "*anddi3_insn"
 104 -  [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
 105 -	(and:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
 106 -		(match_operand:DI 2 "s_register_operand"   "r,r")))]
 107 -  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
 108 -  "#"
 109 -  [(set_attr "length" "8")]
 110 -)
 111 -
 112 -(define_insn_and_split "*anddi_zesidi_di"
 113 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 114 -	(and:DI (zero_extend:DI
 115 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 116 -		(match_operand:DI 1 "s_register_operand" "0,r")))]
 117 -  "TARGET_32BIT"
 118 -  "#"
 119 -  "TARGET_32BIT && reload_completed"
 120 -  ; The zero extend of operand 2 clears the high word of the output
 121 -  ; operand.
 122 -  [(set (match_dup 0) (and:SI (match_dup 1) (match_dup 2)))
 123 -   (set (match_dup 3) (const_int 0))]
 124 -  "
 125    {
 126 -    operands[3] = gen_highpart (SImode, operands[0]);
 127 -    operands[0] = gen_lowpart (SImode, operands[0]);
 128 -    operands[1] = gen_lowpart (SImode, operands[1]);
 129 -  }"
 130 -  [(set_attr "length" "8")]
 131 -)
 132 -
 133 -(define_insn "*anddi_sesdi_di"
 134 -  [(set (match_operand:DI          0 "s_register_operand" "=&r,&r")
 135 -	(and:DI (sign_extend:DI
 136 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 137 -		(match_operand:DI  1 "s_register_operand" "0,r")))]
 138 -  "TARGET_32BIT"
 139 -  "#"
 140 -  [(set_attr "length" "8")]
 141 +    if (!TARGET_NEON && !TARGET_IWMMXT)
 142 +      {
 143 +        rtx low0 = gen_lowpart (SImode, operands[0]);
 144 +	rtx low1 = gen_lowpart (SImode, operands[1]);
 145 +	rtx low2 = gen_lowpart (SImode, operands[2]);
 146 +        rtx high0 = gen_highpart (SImode, operands[0]);
 147 +	rtx high1 = gen_highpart (SImode, operands[1]);
 148 +	rtx high2 = gen_highpart (SImode, operands[2]);
 149 +
 150 +        emit_insn (gen_andsi3 (low0, low1, low2));
 151 +        emit_insn (gen_andsi3 (high0, high1, high2));
 152 +        DONE;
 153 +      }
 154 +  }
 155  )
 156  
 157  (define_expand "andsi3"
 158 @@ -2738,13 +2654,11 @@
 159     (set_attr "predicable" "yes")]
 160  )
 161  
 162 -; constants for op 2 will never be given to these patterns.
 163 -(define_insn_and_split "*anddi_notdi_di"
 164 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 165 -	(and:DI (not:DI (match_operand:DI 1 "s_register_operand" "0,r"))
 166 -		(match_operand:DI 2 "s_register_operand" "r,0")))]
 167 -  "TARGET_32BIT"
 168 -  "#"
 169 +; Splitter for bicdi3_neon
 170 +(define_split
 171 +  [(set (match_operand:DI 0 "s_register_operand" "")
 172 +       (and:DI (not:DI (match_operand:DI 1 "s_register_operand" ""))
 173 +               (match_operand:DI 2 "s_register_operand" "")))]
 174    "TARGET_32BIT && reload_completed
 175     && ! (TARGET_NEON && IS_VFP_REGNUM (REGNO (operands[0])))
 176     && ! IS_IWMMXT_REGNUM (REGNO (operands[0]))"
 177 @@ -2759,58 +2673,6 @@
 178      operands[5] = gen_highpart (SImode, operands[2]);
 179      operands[2] = gen_lowpart (SImode, operands[2]);
 180    }"
 181 -  [(set_attr "length" "8")
 182 -   (set_attr "predicable" "yes")]
 183 -)
 184 -  
 185 -(define_insn_and_split "*anddi_notzesidi_di"
 186 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 187 -	(and:DI (not:DI (zero_extend:DI
 188 -			 (match_operand:SI 2 "s_register_operand" "r,r")))
 189 -		(match_operand:DI 1 "s_register_operand" "0,?r")))]
 190 -  "TARGET_32BIT"
 191 -  "@
 192 -   bic%?\\t%Q0, %Q1, %2
 193 -   #"
 194 -  ; (not (zero_extend ...)) allows us to just copy the high word from
 195 -  ; operand1 to operand0.
 196 -  "TARGET_32BIT
 197 -   && reload_completed
 198 -   && operands[0] != operands[1]"
 199 -  [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
 200 -   (set (match_dup 3) (match_dup 4))]
 201 -  "
 202 -  {
 203 -    operands[3] = gen_highpart (SImode, operands[0]);
 204 -    operands[0] = gen_lowpart (SImode, operands[0]);
 205 -    operands[4] = gen_highpart (SImode, operands[1]);
 206 -    operands[1] = gen_lowpart (SImode, operands[1]);
 207 -  }"
 208 -  [(set_attr "length" "4,8")
 209 -   (set_attr "predicable" "yes")]
 210 -)
 211 -  
 212 -(define_insn_and_split "*anddi_notsesidi_di"
 213 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 214 -	(and:DI (not:DI (sign_extend:DI
 215 -			 (match_operand:SI 2 "s_register_operand" "r,r")))
 216 -		(match_operand:DI 1 "s_register_operand" "0,r")))]
 217 -  "TARGET_32BIT"
 218 -  "#"
 219 -  "TARGET_32BIT && reload_completed"
 220 -  [(set (match_dup 0) (and:SI (not:SI (match_dup 2)) (match_dup 1)))
 221 -   (set (match_dup 3) (and:SI (not:SI
 222 -				(ashiftrt:SI (match_dup 2) (const_int 31)))
 223 -			       (match_dup 4)))]
 224 -  "
 225 -  {
 226 -    operands[3] = gen_highpart (SImode, operands[0]);
 227 -    operands[0] = gen_lowpart (SImode, operands[0]);
 228 -    operands[4] = gen_highpart (SImode, operands[1]);
 229 -    operands[1] = gen_lowpart (SImode, operands[1]);
 230 -  }"
 231 -  [(set_attr "length" "8")
 232 -   (set_attr "predicable" "yes")]
 233  )
 234    
 235  (define_insn "andsi_notsi_si"
 236 @@ -2876,41 +2738,21 @@
 237  	(ior:DI (match_operand:DI 1 "s_register_operand" "")
 238  		(match_operand:DI 2 "neon_logic_op2" "")))]
 239    "TARGET_32BIT"
 240 -  ""
 241 -)
 242 -
 243 -(define_insn "*iordi3_insn"
 244 -  [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
 245 -	(ior:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
 246 -		(match_operand:DI 2 "s_register_operand"   "r,r")))]
 247 -  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
 248 -  "#"
 249 -  [(set_attr "length" "8")
 250 -   (set_attr "predicable" "yes")]
 251 -)
 252 -
 253 -(define_insn "*iordi_zesidi_di"
 254 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 255 -	(ior:DI (zero_extend:DI
 256 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 257 -		(match_operand:DI 1 "s_register_operand" "0,?r")))]
 258 -  "TARGET_32BIT"
 259 -  "@
 260 -   orr%?\\t%Q0, %Q1, %2
 261 -   #"
 262 -  [(set_attr "length" "4,8")
 263 -   (set_attr "predicable" "yes")]
 264 -)
 265 -
 266 -(define_insn "*iordi_sesidi_di"
 267 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 268 -	(ior:DI (sign_extend:DI
 269 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 270 -		(match_operand:DI 1 "s_register_operand" "0,r")))]
 271 -  "TARGET_32BIT"
 272 -  "#"
 273 -  [(set_attr "length" "8")
 274 -   (set_attr "predicable" "yes")]
 275 +  {
 276 +    if (!TARGET_NEON && !TARGET_IWMMXT)
 277 +      {
 278 +        rtx low0 = gen_lowpart (SImode, operands[0]);
 279 +	rtx low1 = gen_lowpart (SImode, operands[1]);
 280 +	rtx low2 = gen_lowpart (SImode, operands[2]);
 281 +        rtx high0 = gen_highpart (SImode, operands[0]);
 282 +	rtx high1 = gen_highpart (SImode, operands[1]);
 283 +	rtx high2 = gen_highpart (SImode, operands[2]);
 284 +
 285 +        emit_insn (gen_iorsi3 (low0, low1, low2));
 286 +        emit_insn (gen_iorsi3 (high0, high1, high2));
 287 +        DONE;
 288 +      }
 289 +  }
 290  )
 291  
 292  (define_expand "iorsi3"
 293 @@ -3016,41 +2858,21 @@
 294  	(xor:DI (match_operand:DI 1 "s_register_operand" "")
 295  		(match_operand:DI 2 "s_register_operand" "")))]
 296    "TARGET_32BIT"
 297 -  ""
 298 -)
 299 -
 300 -(define_insn "*xordi3_insn"
 301 -  [(set (match_operand:DI         0 "s_register_operand" "=&r,&r")
 302 -	(xor:DI (match_operand:DI 1 "s_register_operand"  "%0,r")
 303 -		(match_operand:DI 2 "s_register_operand"   "r,r")))]
 304 -  "TARGET_32BIT && !TARGET_IWMMXT && !TARGET_NEON"
 305 -  "#"
 306 -  [(set_attr "length" "8")
 307 -   (set_attr "predicable" "yes")]
 308 -)
 309 -
 310 -(define_insn "*xordi_zesidi_di"
 311 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 312 -	(xor:DI (zero_extend:DI
 313 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 314 -		(match_operand:DI 1 "s_register_operand" "0,?r")))]
 315 -  "TARGET_32BIT"
 316 -  "@
 317 -   eor%?\\t%Q0, %Q1, %2
 318 -   #"
 319 -  [(set_attr "length" "4,8")
 320 -   (set_attr "predicable" "yes")]
 321 -)
 322 -
 323 -(define_insn "*xordi_sesidi_di"
 324 -  [(set (match_operand:DI 0 "s_register_operand" "=&r,&r")
 325 -	(xor:DI (sign_extend:DI
 326 -		 (match_operand:SI 2 "s_register_operand" "r,r"))
 327 -		(match_operand:DI 1 "s_register_operand" "0,r")))]
 328 -  "TARGET_32BIT"
 329 -  "#"
 330 -  [(set_attr "length" "8")
 331 -   (set_attr "predicable" "yes")]
 332 +  {
 333 +    if (!TARGET_NEON && !TARGET_IWMMXT)
 334 +      {
 335 +        rtx low0 = gen_lowpart (SImode, operands[0]);
 336 +	rtx low1 = gen_lowpart (SImode, operands[1]);
 337 +	rtx low2 = gen_lowpart (SImode, operands[2]);
 338 +        rtx high0 = gen_highpart (SImode, operands[0]);
 339 +	rtx high1 = gen_highpart (SImode, operands[1]);
 340 +	rtx high2 = gen_highpart (SImode, operands[2]);
 341 +
 342 +        emit_insn (gen_xorsi3 (low0, low1, low2));
 343 +        emit_insn (gen_xorsi3 (high0, high1, high2));
 344 +        DONE;
 345 +      }
 346 +  }
 347  )
 348  
 349  (define_expand "xorsi3"
 350 @@ -4355,7 +4177,26 @@
 351    "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)"
 352    "")
 353  
 354 -(define_insn_and_split "one_cmpldi2"
 355 +(define_expand "one_cmpldi2"
 356 +  [(set (match_operand:DI 0 "s_register_operand" "")
 357 +	(not:DI (match_operand:DI 1 "s_register_operand" "")))]
 358 +  "TARGET_32BIT"
 359 +  {
 360 +    if (!TARGET_NEON && !TARGET_IWMMXT)
 361 +      {
 362 +        rtx low0 = gen_lowpart (SImode, operands[0]);
 363 +	rtx low1 = gen_lowpart (SImode, operands[1]);
 364 +        rtx high0 = gen_highpart (SImode, operands[0]);
 365 +	rtx high1 = gen_highpart (SImode, operands[1]);
 366 +
 367 +        emit_insn (gen_one_cmplsi2 (low0, low1));
 368 +        emit_insn (gen_one_cmplsi2 (high0, high1));
 369 +        DONE;
 370 +      }
 371 +  }
 372 +)
 373 +
 374 +(define_insn_and_split "*one_cmpldi2_neon"
 375    [(set (match_operand:DI 0 "s_register_operand"	 "=w,&r,&r,?w")
 376  	(not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))]
 377    "TARGET_32BIT"
 378 @@ -4565,29 +4406,68 @@
 379  
 380  ;; Zero and sign extension instructions.
 381  
 382 -(define_insn "zero_extend<mode>di2"
 383 -  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r")
 384 -        (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
 385 -					    "<qhs_zextenddi_cstr>")))]
 386 -  "TARGET_32BIT <qhs_zextenddi_cond>"
 387 -  "#"
 388 -  [(set_attr "length" "8,4,8")
 389 -   (set_attr "ce_count" "2")
 390 -   (set_attr "predicable" "yes")]
 391 -)
 392 +(define_expand "zero_extend<mode>di2"
 393 +  [(match_operand:DI 0 "s_register_operand" "")
 394 +   (match_operand:QHSI 1 "<qhs_zextenddi_op>" "")]
 395 +  "TARGET_32BIT"
 396 +{
 397 +  if (TARGET_NEON && !reload_completed)
 398 +    emit_insn (gen_zero_extend<mode_name>di2_neon (operands[0], operands[1]));
 399 +  else
 400 +    {
 401 +      rtx lo_part = gen_lowpart (SImode, operands[0]);
 402 +      enum machine_mode src_mode = GET_MODE (operands[1]);
 403 +
 404 +      if (REG_P (operands[0])
 405 +	  && !reg_overlap_mentioned_p (operands[0], operands[1]))
 406 +	emit_clobber (operands[0]);
 407 +      if (!REG_P (lo_part) || src_mode != SImode
 408 +	  || !rtx_equal_p (lo_part, operands[1]))
 409 +	{
 410 +	  if (src_mode == SImode)
 411 +	    emit_move_insn (lo_part, operands[1]);
 412 +	  else
 413 +	    emit_insn (gen_rtx_SET (VOIDmode, lo_part,
 414 +				    gen_rtx_ZERO_EXTEND (SImode, operands[1])));
 415 +	}
 416  
 417 -(define_insn "extend<mode>di2"
 418 -  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r")
 419 -        (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
 420 -					    "<qhs_extenddi_cstr>")))]
 421 -  "TARGET_32BIT <qhs_sextenddi_cond>"
 422 -  "#"
 423 -  [(set_attr "length" "8,4,8,8")
 424 -   (set_attr "ce_count" "2")
 425 -   (set_attr "shift" "1")
 426 -   (set_attr "predicable" "yes")
 427 -   (set_attr "arch" "*,*,a,t")]
 428 -)
 429 +      emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx);
 430 +    }
 431 +  DONE;
 432 +})
 433 +
 434 +(define_expand "extend<mode>di2"
 435 +  [(match_operand:DI 0 "s_register_operand" "")
 436 +   (match_operand:QHSI 1 "<qhs_extenddi_op>" "")]
 437 +  "TARGET_32BIT"
 438 +{
 439 +  if (TARGET_NEON && !reload_completed)
 440 +    emit_insn (gen_extend<mode_name>di2_neon (operands[0], operands[1]));
 441 +  else
 442 +    {
 443 +      rtx lo_part = gen_lowpart (SImode, operands[0]);
 444 +      enum machine_mode src_mode = GET_MODE (operands[1]);
 445 +
 446 +      if (REG_P (operands[0])
 447 +	  && !reg_overlap_mentioned_p (operands[0], operands[1]))
 448 +	emit_clobber (operands[0]);
 449 +
 450 +      if (!REG_P (lo_part) || src_mode != SImode
 451 +	  || !rtx_equal_p (lo_part, operands[1]))
 452 +	{
 453 +	  if (src_mode == SImode)
 454 +	    emit_move_insn (lo_part, operands[1]);
 455 +	  else
 456 +	    emit_insn (gen_rtx_SET (VOIDmode, lo_part,
 457 +				    gen_rtx_SIGN_EXTEND (SImode, operands[1])));
 458 +	  operands[1] = lo_part;
 459 +	}
 460 +      operands[0] = gen_highpart (SImode, operands[0]);
 461 +      emit_insn (gen_ashrsi3 (operands[0], operands[1],
 462 +			      gen_rtx_CONST_INT (VOIDmode, 31)));
 463 +    }
 464 +  DONE;
 465 +})
 466  
 467  ;; Splits for all extensions to DImode
 468  (define_split
 469 @@ -4596,26 +4476,23 @@
 470    "TARGET_32BIT && (!TARGET_NEON
 471  		    || (reload_completed
 472  			&& !(IS_VFP_REGNUM (REGNO (operands[0])))))"
 473 -  [(set (match_dup 0) (match_dup 1))]
 474 +  [(const_int 0)]
 475  {
 476 -  rtx lo_part = gen_lowpart (SImode, operands[0]);
 477 -  enum machine_mode src_mode = GET_MODE (operands[1]);
 478 -
 479 -  if (REG_P (operands[0])
 480 -      && !reg_overlap_mentioned_p (operands[0], operands[1]))
 481 -    emit_clobber (operands[0]);
 482 -  if (!REG_P (lo_part) || src_mode != SImode
 483 -      || !rtx_equal_p (lo_part, operands[1]))
 484 +  switch (GET_MODE (operands[1]))
 485      {
 486 -      if (src_mode == SImode)
 487 -        emit_move_insn (lo_part, operands[1]);
 488 -      else
 489 -        emit_insn (gen_rtx_SET (VOIDmode, lo_part,
 490 -				gen_rtx_ZERO_EXTEND (SImode, operands[1])));
 491 -      operands[1] = lo_part;
 492 +    case SImode:
 493 +      emit_insn (gen_zero_extendsidi2 (operands[0], operands[1]));
 494 +      break;
 495 +    case HImode:
 496 +      emit_insn (gen_zero_extendhidi2 (operands[0], operands[1]));
 497 +      break;
 498 +    case QImode:
 499 +      emit_insn (gen_zero_extendqidi2 (operands[0], operands[1]));
 500 +      break;
 501 +    default:
 502 +      gcc_unreachable ();
 503      }
 504 -  operands[0] = gen_highpart (SImode, operands[0]);
 505 -  operands[1] = const0_rtx;
 506 +  DONE;
 507  })
 508  
 509  (define_split
 510 @@ -4624,26 +4501,23 @@
 511    "TARGET_32BIT && (!TARGET_NEON
 512  		    || (reload_completed
 513  			&& !(IS_VFP_REGNUM (REGNO (operands[0])))))"
 514 -  [(set (match_dup 0) (ashiftrt:SI (match_dup 1) (const_int 31)))]
 515 +  [(const_int 0)]
 516  {
 517 -  rtx lo_part = gen_lowpart (SImode, operands[0]);
 518 -  enum machine_mode src_mode = GET_MODE (operands[1]);
 519 -
 520 -  if (REG_P (operands[0])
 521 -      && !reg_overlap_mentioned_p (operands[0], operands[1]))
 522 -    emit_clobber (operands[0]);
 523 -
 524 -  if (!REG_P (lo_part) || src_mode != SImode
 525 -      || !rtx_equal_p (lo_part, operands[1]))
 526 +  switch (GET_MODE (operands[1]))
 527      {
 528 -      if (src_mode == SImode)
 529 -        emit_move_insn (lo_part, operands[1]);
 530 -      else
 531 -        emit_insn (gen_rtx_SET (VOIDmode, lo_part,
 532 -				gen_rtx_SIGN_EXTEND (SImode, operands[1])));
 533 -      operands[1] = lo_part;
 534 +    case SImode:
 535 +      emit_insn (gen_extendsidi2 (operands[0], operands[1]));
 536 +      break;
 537 +    case HImode:
 538 +      emit_insn (gen_extendhidi2 (operands[0], operands[1]));
 539 +      break;
 540 +    case QImode:
 541 +      emit_insn (gen_extendqidi2 (operands[0], operands[1]));
 542 +      break;
 543 +    default:
 544 +      gcc_unreachable ();
 545      }
 546 -  operands[0] = gen_highpart (SImode, operands[0]);
 547 +  DONE;
 548  })
 549  
 550  (define_expand "zero_extendhisi2"
 551 diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md
 552 index bda77f8..9f97d66 100644
 553 --- a/gcc/config/arm/iterators.md
 554 +++ b/gcc/config/arm/iterators.md
 555 @@ -187,6 +187,8 @@
 556  ;; Mode attributes
 557  ;;----------------------------------------------------------------------------
 558  
 559 +(define_mode_attr mode_name [(SI "si") (HI "hi") (QI "qi")])
 560 +
 561  ;; Determine element size suffix from vector mode.
 562  (define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")])
 563  
 564 @@ -400,9 +402,6 @@
 565  (define_mode_attr V_unpack   [(V16QI "V8HI") (V8HI "V4SI") (V4SI "V2DI")])
 566  
 567  ;; Conditions to be used in extend<mode>di patterns.
 568 -(define_mode_attr qhs_zextenddi_cond [(SI "") (HI "&& arm_arch6") (QI "")])
 569 -(define_mode_attr qhs_sextenddi_cond [(SI "") (HI "&& arm_arch6")
 570 -				      (QI "&& arm_arch6")])
 571  (define_mode_attr qhs_zextenddi_op [(SI "s_register_operand")
 572  				   (HI "nonimmediate_operand")
 573  				   (QI "nonimmediate_operand")])
 574 diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md
 575 index a33dbd2..8f8a0c5 100644
 576 --- a/gcc/config/arm/neon.md
 577 +++ b/gcc/config/arm/neon.md
 578 @@ -5991,6 +5991,30 @@
 579  
 580  ;; Copy from core-to-neon regs, then extend, not vice-versa
 581  
 582 +(define_insn "zero_extend<mode>di2_neon"
 583 +  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r")
 584 +        (zero_extend:DI (match_operand:QHSI 1 "<qhs_zextenddi_op>"
 585 +					    "<qhs_zextenddi_cstr>")))]
 586 +  "TARGET_NEON"
 587 +  "#"
 588 +  [(set_attr "length" "8,4,8")
 589 +   (set_attr "ce_count" "2")
 590 +   (set_attr "predicable" "yes")]
 591 +)
 592 +
 593 +(define_insn "extend<mode>di2_neon"
 594 +  [(set (match_operand:DI 0 "s_register_operand" "=w,r,?r,?r")
 595 +        (sign_extend:DI (match_operand:QHSI 1 "<qhs_extenddi_op>"
 596 +					    "<qhs_extenddi_cstr>")))]
 597 +  "TARGET_NEON"
 598 +  "#"
 599 +  [(set_attr "length" "8,4,8,8")
 600 +   (set_attr "ce_count" "2")
 601 +   (set_attr "shift" "1")
 602 +   (set_attr "predicable" "yes")
 603 +   (set_attr "arch" "*,*,a,t")]
 604 +)
 605 +
 606  (define_split
 607    [(set (match_operand:DI 0 "s_register_operand" "")
 608  	(sign_extend:DI (match_operand:SI 1 "s_register_operand" "")))]

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  • [get | view] (2012-05-29 02:24:58, 18.3 KB) [[attachment:core-and64-2.patch]]
  • [get | view] (2012-05-22 14:26:35, 19.6 KB) [[attachment:core-and64.patch]]
  • [get | view] (2012-05-25 09:12:50, 0.7 KB) [[attachment:lowersubreg.patch]]
  • [get | view] (2012-05-30 07:08:18, 6.1 KB) [[attachment:neon-and64.patch]]
  • [get | view] (2012-05-30 03:33:51, 3.0 KB) [[attachment:neon-muldi3.patch]]
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