Individual blueprints that have been registered.
Track and reduce performance regressions
There is to some extent a dependency on systematic benchmarking of upstream trunk to make sure regressions upstream are caught early for configurations we care about.
Retain currently in original blueprint
Work items (Condexec): Improve cond-exec code generation (2w): TODO Tune BRANCH_COST properly (1w): TODO Investigate effect of reducing long latency conditional instructions for A9 (1w): TODO Implement (1w): TODO Benchmark (1w): TODO
Work Items (widening multiply): Improve code generated for 64 bit widening multiply from 16 bit operations: TODO Improve code generated for 64 bit widening multiply and accumulate from 16 bit operations: TODO Discuss with upstream: TODO Backport to linaro 4.5: TODO Backport to Linaro 4.6: TODO
Not yet classified
Work items: Improve constant generation in Thumb2 (2w): INPROGRESS Reduce the amount of redundant stores from VFP to ARM Core registers (2w): TODO Investigate current constant pool generation / placement : TODO 2w Investigate the register allocator with respect to choice of Thumb1 vs Thumb2 instructions as discussed in the TSC commentary: TODO 3w Upstreaming cost and Backporting cost is estimated to be very aggressively at about 1w of effort per "implements" work item which adds up to about 8-9w of effort overall ?
RamanaRadhakrishnan/Sandbox/11PerfPlanEstimates (last modified 2011-05-27 13:27:56)